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precision instrumentation amplifier ad524 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features low noise: 0.3 v p-p at 0.1 hz to 10 hz low nonlinearity: 0.003% (g = 1) high cmrr: 120 db (g = 1000) low offset voltage: 50 v low offset voltage drift: 0.5 v/c gain bandwidth product: 25 mhz pin programmable gains of 1, 10, 100, 1000 input protection, power-on/power-off no external components required internally compensated mil-std-883b and chips available 16-lead ceramic dip and soic packages and 20-terminal leadless chip carrier available available in tape and reel in accordance with eia-481a standard standard military drawing also available functional block diagram ad524 20k? ? input g = 10 + input g = 100 g = 1000 4.44k ? 404? 40 ? protection 20k? 20k ? 20k ? 20k? 20k? sense reference protection rg 1 rg 2 1 13 12 11 16 3 2 v b output 00500-001 figure 1. general description the ad524 is a precision monolithic instrumentation amplifier designed for data acquisition applications requiring high accu- racy under worst-case operating conditions. an outstanding combination of high linearity, high common-mode rejection, low offset voltage drift, and low noise makes the ad524 suitable for use in many data acquisition systems. the ad524 has an output offset voltage drift of less than 25 v/c, input offset voltage drift of less than 0.5 v/c, cmr above 90 db at unity gain (120 db at g = 1000), and maximum nonlinearity of 0.003% at g = 1. in addition to the outstanding dc specifications, the ad524 also has a 25 khz bandwidth (g = 1000). to make it suitable for high speed data acquisition systems, the ad524 has an output slew rate of 5 v/s and settles in 15 s to 0.01% for gains of 1 to 100. as a complete amplifier, the ad524 does not require any exter- nal components for fixed gains of 1, 10, 100 and 1000. for other gain settings between 1 and 1000, only a single resistor is required. the ad524 input is fully protected for both power-on and power-off fault conditions. the ad524 ic instrumentation amplifier is available in four different versions of accuracy and operating temperature range. the economical a grade, the low drift b grade, and lower drift, higher linearity c grade are specified from ?25c to +85c. the s grade guarantees performance to specification over the extended temperature range ?55c to +125c. the ad524 is available in a 16-lead ceramic dip, 16-lead sbdip, 16-lead soic wide packages, and 20-terminal leadless chip carrier. product highlights 1. the ad524 has guaranteed low offset voltage, offset voltage drift, and low noise for precision high gain applications. 2. the ad524 is functionally complete with pin program- mable gains of 1, 10, 100, and 1000, and single resistor programmable for any gain. 3. input and output offset nulling terminals are provided for very high precision applications and to minimize offset voltage changes in gain ranging applications. 4. the ad524 is input protected for both power-on and power-off fault conditions. 5. the ad524 offers superior dynamic performance with a gain bandwidth product of 25 mhz, full power response of 75 khz and a settling time of 15 s to 0.01% of a 20 v step (g = 100).
ad524* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts documentation application notes ? an-202: an ic amplifier user?s guide to decoupling, grounding, and making things go right for a change ? an-244: a user's guide to i.c. instrumentation amplifiers ? an-245: instrumentation amplifiers solve unusual design problems ? an-282: fundamentals of sampled data systems ? an-306: synchronous system measures s ? an-307: modem-circuit techniques simplify instrumentation designs ? an-589: ways to optimize the performance of a difference amplifier ? an-671: reducing rfi rectification errors in in-amp circuits data sheet ? ad524 military data sheet ? ad524: precision instrumentation amplifier data sheet technical books ? a designer's guide to instrumentation amplifiers, 3rd edition, 2006 tools and simulations ? in-amp error calculator reference materials technical articles ? auto-zero amplifiers ? high-performance adder uses instrumentation amplifiers ? input filter prevents instrumentation-amp rf-rectification errors ? the ad8221 - setting a new industry standard for instrumentation amplifiers design resources ? ad524 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad524 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ad524 rev. f | page 2 of 28 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 8 connection diagrams .................................................................. 8 esd caution .................................................................................. 8 typical performance characteristics ............................................. 9 test circuits ................................................................................. 14 theory of operation ...................................................................... 15 input protection .......................................................................... 15 input offset and output offset ................................................ 15 gain .............................................................................................. 16 input bias currents .................................................................... 17 common-mode rejection ........................................................ 17 grounding ................................................................................... 18 sense terminal ............................................................................ 18 reference terminal .................................................................... 18 programmable gain ................................................................... 20 autozero circuits ....................................................................... 20 error budget analysis ................................................................ 21 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 25 revision history 11/07rev. e to rev. f updated format .................................................................. universal changes to general description .................................................... 1 changes to figure 1 .......................................................................... 1 changes to figure 3 and figure 4 captions .................................. 8 changes to error budget analysis section ................................. 21 changes to ordering guide .......................................................... 25 4/99rev. d to rev. e
ad524 rev. f | page 3 of 28 specifications @ v s = 15 v, r l = 2 k and t a = +25c, unless otherwise noted. all min and max specifications are guaranteed. specifications shown in boldface are tested on all production units at the final electrical test. results from those tests are used to calculate outgoing quality levels. table 1. ad524a ad524b parameter min typ max min typ max unit gain gain equation (external resistor gain programming) %201 000,40 ? ? ? ? ? ? + g r %201 000,40 ? ? ? ? ? ? + g r gain range (pin programmable) 1 to 1000 1 to 1000 gain error 1 g = 1 0.05 0.03 % g = 10 0.25 0.15 % g = 100 0.5 0.35 % g = 1000 2.0 1.0 % nonlinearity g = 1 0.01 0.005 % g = 10, g = 100 0.01 0.005 % g = 1000 0.01 0.01 % gain vs. temperature g = 1 5 5 ppm/c g = 10 15 10 ppm/c g = 100 35 25 ppm/c g = 1000 100 50 ppm/c voltage offset (may be nulled) input offset voltage 250 100 v vs. temperature 2 0.75 v/c output offset voltage 5 3 mv vs. temperature 100 50 v offset referred to the input vs. supply g = 1 70 75 db g = 10 85 95 db g = 100 95 105 db g = 1000 100 110 db input current input bias current 50 25 na vs. temperature 100 100 pa/c input offset current 35 15 na vs. temperature 100 100 pa/c
ad524 rev. f | page 4 of 28 ad524a ad524b parameter min typ max min typ max unit input input impedance differential resistance 10 9 10 9 differential capacitance 10 10 pf common-mode resistance 10 9 10 9 common-mode capacitance 10 10 pf input voltage range maximum differential input linear (v dl ) 2 10 10 v maximum common-mode linear (v cm ) 2 ? ? ? ? ? ? ? d v 2 g v12 ? ? ? ? ? ? ? d v 2 g v12 v common-mode rejection dc to 60 hz with 1 k source imbalance v g = 1 70 75 db g = 10 90 95 db g = 100 100 105 db g = 1000 110 115 db output rating v out , r l = 2 k 10 10 v dynamic response small signal C 3 db g = 1 1 1 mhz g = 10 400 400 khz g = 100 150 150 khz g = 1000 25 25 khz slew rate 5.0 5.0 v/s settling time to 0.01%, 20 v step g = 1 to 100 15 15 s g = 1000 75 75 s noise voltage noise, 1 khz rti 7 7 nv/hz rto 90 90 nvhz rti, 0.1 hz to 10 hz g = 1 15 15 v p-p g = 10 2 2 v p-p g = 100, 1000 0.3 0.3 v p-p current noise 0.1 hz to 10 hz 60 60 pa p-p sense input r in 20 20 k 20% i in 15 15 a voltage range 10 10 v gain to output 1 1 % reference input r in 40 40 k 20% i in 15 15 a voltage range 10 10 v gain to output 1 1 %
ad524 rev. f | page 5 of 28 ad524a ad524b parameter min typ max min typ max unit temperature range specified performance C25 +85 C25 +85 c storage C65 +150 C65 +150 c power supply power supply range 6 15 18 6 15 18 v quiescent current 3.5 5.0 3.5 5.0 ma 1 does not include effects of external resistor, r g . 2 v ol is the maximum differential input voltage at g = 1 fo r specified nonlinearity. v dl at the maximum = 10 v/g. v d = actual differential input voltage. example: g = 10, v d = 0.50. v cm = 12 v ? (10/2 0.50 v) = 9.5 v. @ v s = 15 v, r l = 2 k and t a = +25c, unless otherwise noted. all min and max specifications are guaranteed. specifications shown in boldface are tested on all production units at the final electrical test. results from those tests are used to calculate outgoing quality levels. table 2. ad524c ad524s parameter min typ max min typ max unit gain gain equation (external resistor gain programming) %201 000,40 ? ? ? ? ? ? + g r %201 000,40 ? ? ? ? ? ? + g r gain range (pin programmable) 1 to 1000 1 to 1000 gain error 1 g = 1 0.02 0.05 % g = 10 0.1 0.25 % g = 100 0.25 0.5 % g = 1000 0.5 2.0 % nonlinearity g = 1 0.003 0.01 % g = 10, g = 100 0.003 0.01 % g = 1000 0.01 0.01 % gain vs. temperature g = 1 5 5 ppm/c g = 10 10 10 ppm/c g = 100 25 25 ppm/c g = 1000 50 50 ppm/c voltage offset (may be nulled) input offset voltage 50 100 v vs. temperature 0.5 2.0 v/c output offset voltage 2.0 3.0 mv vs. temperature 25 50 v offset referred to the input vs. supply g = 1 80 75 db g = 10 100 95 db g = 100 110 105 db g = 1000 115 110 db
ad524 rev. f | page 6 of 28 ad524c ad524s parameter min typ max min typ max unit input current input bias current 15 50 na vs. temperature 100 100 pa/c input offset current 10 35 na vs. temperature 100 100 pa/c input input impedance differential resistance 10 9 10 9 differential capacitance 10 10 pf common-mode resistance 10 9 10 9 common-mode capacitance 10 10 pf input voltage range maximum differential input linear (v dl ) 2 10 10 v maximum common-mode linear (v cm ) 2 ? ? ? ? ? ? ? d v 2 g v12 ? ? ? ? ? ? ? d v 2 g v12 v common-mode rejection dc to 60 hz with 1 k source imbalance v g = 1 80 70 db g = 10 100 90 db g = 100 110 100 db g = 1000 120 110 db output rating v out , r l = 2 k 10 10 v dynamic response small signal C 3 db g = 1 1 1 mhz g = 10 400 400 khz g = 100 150 150 khz g = 1000 25 25 khz slew rate 5.0 5.0 v/s settling time to 0.01%, 20 v step g = 1 to 100 15 15 s g = 1000 75 75 s noise voltage noise, 1 khz rti 7 7 nv/hz rto 90 90 nvhz rti, 0.1 hz to 10 hz g = 1 15 15 v p-p g = 10 2 2 v p-p g = 100, 1000 0.3 0.3 v p-p current noise 0.1 hz to 10 hz 60 60 pa p-p sense input r in 20 20 k 20% i in 15 15 a voltage range 10 10 v gain to output 1 1 %
ad524 rev. f | page 7 of 28 ad524c ad524s parameter min typ max min typ max unit reference input r in 40 40 k 20% i in 15 15 a voltage range 10 10 v gain to output 1 1 % temperature range specified performance C25 +85 C55 +85 c storage C65 +150 C65 +150 c power supply power supply range 6 15 18 6 15 18 v quiescent current 3.5 5.0 3.5 5.0 ma 1 does not include effects of external resistor r g . 2 v ol is the maximum differential input voltage at g = 1 fo r specified nonlinearity. v dl at the maximum = 10 v/g. v d = actual differential input voltage. example: g = 10, v d = 0.50. v cm = 12 v ? (10/2 0.50 v) = 9.5 v.
ad524 rev. f | page 8 of 28 absolute maximum ratings table 3. parameter rating supply voltage 18 v internal power dissipation 450 mw input voltage 1 (either input simultaneously) |v in | + |v s | <36 v output short-circuit duration indefinite storage temperature range (r) C65c to +125c (d, e) C65c to +150c operating temperature range ad524a/ad524b/ad524c C25c to +85c ad524s C55c to +125c lead temperature (soldering, 60 sec) +300c 1 maximum input voltage specification refers to maximum voltage to which either input terminal may be raised wi th or without device power applied. for example, with 18 volt supplies maximum, v in is 18 v; with zero supply voltage maximum, v in is 36 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rg 1 16 ?input 1 +input 2 rg 2 3 4 input null 5 input null 6 reference 9 output 8 +v s 7 ?v s sense 10 g = 1000 11 g = 100 12 g = 10 13 output null 14 o utput null 15 0.170 (4.33) 0.103 (2.61) pad numbers correspond to pin numbers for the d-16 and rw-16 16-lead ceramic packages. 00500-002 figure 2. metallization photograph contact factory for latest dimensions; dimensions shown in inches and (mm) connection diagrams 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ? input + input input null input null reference output null output null g = 10 g = 100 g = 1000 sense output ad524 rg 2 rg 1 ?v s ?v s +v s +v s short to rg 2 for desired gain 415 514 output offset null input offset null top view (not to scale) 0 0500-003 figure 3. ceramic (d) and soic (rw-16 and d-16) packages short t o rg 2 for desired gain 4 rg 2 5 input null 6 nc 7 input null 8 reference 18 output null 17 g = 10 16 nc 15 g = 100 14 g = 1000 19 rg 1 20 output null 1 nc 2 ?input 3 +input 13 sense 12 output 11 nc 10 +v s 9 ?v s nc = no connect ad524 top view (not to scale) +v s ?v s input offset null output offset null 719 518 00500-004 figure 4. leadless chip carrier (e) esd caution
ad524 rev. f | page 9 of 28 typical performance characteristics 20 15 10 5 0 0 5 10 15 20 supply voltage (v) input voltage (v) +25c 00500-005 figure 5. input voltage range vs. supply voltage, g = 1 20 15 10 5 0 0 5 10 15 20 supply voltage (v) output voltage swing (v) 00500-006 figure 6. output voltage swing vs. supply voltage 30 20 10 0 10 100 1k 10k load resistance ( ? ) output voltage swing (v p-p) 00500-007 figure 7. output voltage swing vs. load resistance 8 6 4 2 0 0 5 10 15 20 supply voltage (v) quiescent current (ma) 00500-008 figure 8. quiescent current vs. supply voltage 16 12 8 4 14 10 6 2 0 0 5 10 15 20 supply voltage (v) input bias current (na) 00500-009 figure 9. input bias current vs. supply voltage 40 20 0 ?20 30 10 ?10 ?30 ?40 ?75 ?25 25 75 125 temperature (c) input bias current (na) 00500-010 figure 10. input bias current vs. temperature
ad524 rev. f | page 10 of 28 16 12 8 4 14 10 6 2 0 0 5 10 15 20 input voltage (v) input bias current (na) 00500-011 figure 11. input bias current vs. input voltage 1 3 5 0 2 4 6 0246 1357 warm-up time (minutes) v os from final value (v) 8 00500-012 figure 12. offset voltage, rti, turn-on drift 100 1 1000 10 0 100 10k 1m 10 1k 100k 10m frequency (hz) gain (v/v) 00500-013 figure 13. gain vs. frequency ?120 ?80 ? 140 ?100 ?40 0 ?60 ?20 0 100 10k 1m 10 1k 100k 10m frequency (hz) cmrr (db) g = 1000 g = 100 g = 10 g = 1 00500-014 figure 14. cmrr vs. frequency, rti, zero to 1000 source imbalance 30 20 10 0 1k 10k 100k 1m frequency (hz) full power response (v p-p) g = 1, 10, 100 00500-015 bandwidth limited g = 1000 g = 100 g = 10 figure 15. large signal frequency response 10 6 8 4 2 0 1 10 100 1000 gain (v/v) slew rate (v/s) g = 1000 00500-016 figure 16. slew rate vs. gain
ad524 rev. f | page 11 of 28 120 80 140 160 100 40 0 60 20 100 10k 10 1k 100k frequency (hz) power supply rejection ratio (db) g = 1 0 0 0 g = 1 0 g = 1 g = 1 0 0 +v s = 15v dc + 1v p-p sinewave 00500-017 figure 17. positive psrr vs. frequency 120 80 140 160 100 40 0 60 20 100 10k 10 1k 100k frequency (hz) power supply rejection ratio (db) g = 1 0 0 g = 1 0 g = 1 g = 1 0 0 0 ?v s = ?15v dc + 1v p-p sinewave 00500-018 figure 18. negative psrr vs. frequency 1000 0.1 1 100k frequency (hz) volt nsd (nv/ hz) 10 100 1k 10k 1 10 100 g = 1000 g = 100, 1000 g = 10 g = 1 00500-019 figure 19. rti noise spectral density vs. gain 100k 0 10k frequency (hz) current noise spectral density (fa/ hz) 1 10 100 1k 100 1k 10k 00500-020 figure 20. input current noise vs. frequency 0.1hz to 10hz vertical scale; 1 division = 5v 5mv 1s 00500-021 figure 21. low frequency noise, g = 1 (system gain = 1000) 0.1hz to 10hz vertical scale; 1 division = 0.1v 10mv 1s 00500-022 figure 22. low frequency noise, g = 1000 (system gain = 100,000)
ad524 rev. f | page 12 of 28 ?12 to +12 +4 to ?4 +8 to ?8 +12 to ?12 ?8 to +8 ?4 to +4 1% 0.1% 0.01% 1% 0.1% 0.01% output step (v) settling time (s) 0 5 10 15 20 00500-023 figure 23. settling time, gain = 1 10v 10s 1mv 00500-024 figure 24. large signal pulse response and settling time, gain =1 ?12 to +12 +4 to ?4 +8 to ?8 +12 to ?12 ?8 to +8 ?4 to +4 0.01% 0.01% output step (v) 0.1% 1% 1% 0.1% settling time (s) 0 5 10 15 20 00500-025 figure 25. settling time, gain = 10 1mv 10v 10s 0 0500-026 figure 26. large signal pulse response and settling time, gain = 10 ? 12 to +12 +4 to ?4 +8 to ?8 +12 to ?12 ?8 to +8 ?4 to +4 output step (v) 1% 1% 0.01% 0.01% 0.1% 0.1% settling time (s) 0 5 10 15 20 00500-027 figure 27. settling time, gain = 100 1mv 10v 10s 0 0500-028 figure 28. large signal pulse response and settling time, gain = 100
ad524 rev. f | page 13 of 28 ?12 to +12 +4 to ?4 +8 to ?8 +12 to ?12 ?8 to +8 ?4 to +4 output step (v) 1% 0.01% 1% 0.01% 0.1% 0.1% 0 102030405060708 settling time (s) 00500-029 0 figure 29. settling time, gain = 1000 5mv 10v 20s 0 0500-030 figure 30. large signal pulse response and settling time, gain = 1000
ad524 rev. f | page 14 of 28 test circuits ad524 g = 10 g = 100 g = 1000 10k? 0.01% 1k? 10t 10k ? 0.1% v out +v s ? + input 20v p-p 11k? 0.1% 1k? 0.1% 100 ? 0.1% ?v s rg 1 rg 2 100k ? 0.1% 1 16 13 12 9 11 10 6 3 8 7 2 00500-031 figure 31. settling time test circuit ?in c4 c3 +in reference sense a3 4.44k ? 404? 40? g = 100 g = 1000 q2, q4 q1, q3 +v s i 1 50a i 2 50a a1 a2 r52 20k? r55 20k? v o ch 1 i 4 50a ?v s i 3 50a v b r53 20k? r54 20k? ch 2 , ch 3 , ch 4 rg 2 rg 1 ch 1 ch 2 , ch 3 , ch 4 r57 20k? r56 20k? ++ 00500-032 figure 32. simplified circuit of amplifier; gain is defined as ((r56 + r57)/(r g )) +1; for a gain of 1, r g is an open circuit
ad524 rev. f | page 15 of 28 theory of operation the ad524 is a monolithic instrumentation amplifier based on the classic 3-op amp circuit. the advantage of monolithic construction is the closely matched components that enhance the performance of the input preamplifier. the preamplifier section develops the programmed gain by the use of feedback concepts. the programmed gain is developed by varying the value of r g (smaller values increase the gain) while the feedback forces the collector currents (q1, q2, q3, and q4) to be constant, which impresses the input voltage across r g . as r g is reduced to increase the programmed gain, the transconductance of the input preamplifier increases to the transconductance of the input transistors. this has three important advantages. first, this approach allows the circuit to achieve a very high open-loop gain of 3 10 8 at a programmed gain of 1000, thus reducing gain-related errors to a negligible 30 ppm. second, the gain bandwidth product, which is deter- mined by c3 or c4 and the input transconductance, reaches 25 mhz. third, the input voltage noise reduces to a value determined by the collector current of the input transistors for an rti noise of 7 nv/hz at g = 1000. input protection as interface amplifiers for data acquisition systems, instru- mentation amplifiers are often subjected to input overloads, that is, voltage levels in excess of the full scale for the selected gain range. at low gains (10 or less), the gain resistor acts as a current limiting element in series with the inputs. at high gains, the lower value of r g does not adequately protect the inputs from excessive currents. standard practice is to place series limiting resistors in each input, but to limit input current to below 5 ma with a full differential overload (36 v) requires over 7k of resistance, which adds 10 nvhz of noise. to provide both input protection and low noise, a special series protection fet is used. a unique fet design was used to provide a bidirectional current limit, thereby protecting against both positive and negative overloads. under nonoverload conditions, three channels (ch 2 , ch 3 , ch 4 ) act as a resistance (1 k) in series with the input as before. during an overload in the positive direction, a fourth channel, ch 1 , acts as a small resistance (3 k) in series with the gate, which draws only the leakage current, and the fet limits i dss . when the fet enhances under a negative overload, the gate current must go through the small fet formed by ch 1 and when this fet goes into saturation, the gate current is limited and the main fet goes into controlled enhancement. the bidirectional limiting holds the maximum input current to 3 ma over the 36 v range. input offset and output offset voltage offset specifications are often considered a figure of merit for instrumentation amplifiers. while initial offset may be adjusted to zero, shifts in offset voltage due to temperature variations causes errors. intelligent systems can often correct this factor with an autozero cycle, but there are many small- signal high-gain applications that do not have this capability. +v s rg 2 ad712 1/2 9.09k ? 1k ? 100 ? 16.2k ? 1/2 16.2k ? 1.62m ? 1.82k ? 10 100 1000 g = 1, 10, 100 g = 1000 ad524 + v s ? + ?v s 1 16 13 12 9 11 10 6 3 8 7 2 1f 1f ?v s 1f 3 2 8 1 5 6 4 7 0 0500-033 + ? + ? figure 33. noise test circuit
ad524 rev. f | page 16 of 28 voltage offset and drift comprise two components each; input and output offset and offset drift. input offset is the component of offset that is directly proportional to gain, that is, input offset as measured at the output at g = 100 is 100 times greater than at g = 1. output offset is independent of gain. at low gains, output offset drift is dominant, at high gains, input offset drift dominates. therefore, the output offset voltage drift is normally specified as drift at g = 1 (where input effects are insignificant), whereas input offset voltage drift is given by drift specification at a high gain (where output offset effects are negligible). all input related numbers are referred to the input (rti) that is the effect on the output is g times larger. voltage offset vs. power supply is also specified at one or more gain settings and is also rti. by separating these errors, one can evaluate the total error independent of the gain setting used. in a given gain configura- tion, both errors can be combined to give a total error referred to the input (rti) or output (rto) by the following formulas: total error rti = input error + ( output error/gain ) total error rto = (g ain input error ) + output error as an illustration, a typical ad524 might have a +250 v output offset and a ?50 v input offset. in a unity gain configuration, the total output offset would be 200 v or the sum of the two. at a gain of 100, the output offset would be ?4.75 mv or: +250 v + 100(?50 v) = ?4.75 mv. the ad524 provides for both input and output offset adjustment. this simplifies very high precision applications and minimizes offset voltage changes in switched gain applications. in such applications, the input offset is adjusted first at the highest programmed gain, then the output offset is adjusted at g = 1. gain the ad524 has internal high accuracy pretrimmed resistors for pin programmable gains of 1, 10, 100, and 1000. one of the preset gains can be selected by pin strapping the appropriate gain terminal and rg 2 together (for g = 1, rg 2 is not connected). ad524 g = 10 g = 100 g = 1000 +input ? input v out output signal common ?v s input offset null +v s 10k? rg 1 rg 2 1 16 13 12 11 3 2 8 4 5 10 9 6 7 00500-034 figure 34. operating connections for g = 100 the ad524 can be configured for gains other than those that are internally preset; there are two methods to do this. the first method uses just an external resistor connected between pin 3 and pin 16 (see figure 35 ), which programs the gain according to the following formula: 1 k40 : g r g for best results, r g should be a precision resistor with a low temperature coefficient. an external r g affects both gain accuracy and gain drift due to the mismatch between it and the internal thin-film resistors. gain accuracy is determined by the tolerance of the external r g and the absolute accuracy of the internal resistors (20%). gain drift is determined by the mismatch of the temperature coefficient of r g and the tempera- ture coefficient of the internal resistors (?50 ppm/c typical). 40,000 2.105 g = + 1 = 20 20% ad524 reference 1k ? +input ?input 2.105k ? 1.5k ? v out + v s ?v s rg 1 rg 2 1 16 8 7 6 9 10 13 12 11 3 2 00500-035 figure 35. operating connections for g = 20 the second method uses the internal resistors in parallel with an external resistor (see figure 36 ). this technique minimizes the gain adjustment range and reduces the effects of tempera- ture coefficient sensitivity. g = g = 10 ad524 reference +input ?input 4k? *r| g = 10 = 4444.44 ? *r| g = 100 = 404.04 ? *r| g = 1000 = 40.04 ? *nominal (20%) v out 40,000 4000||4444.44 + 1 = 20 17% + v s ?v s rg 1 rg 2 1 16 13 12 11 3 2 8 7 10 6 9 00500-036 figure 36. operating connections for g = 20, low gain temperature coefficient technique
ad524 rev. f | page 17 of 28 the ad524 can also be configured to provide gain in the output stage. figure 37 shows an h pad attenuator connected to the reference and sense lines of the ad524. r1, r2, and r3 should be made as low as possible to minimize the gain variation and reduction of cmrr. varying r2 precisely sets the gain without affecting cmrr. cmrr is determined by the match of r1 and r3. g = 100 g = 1000 g = g = 10 ad524 +input ?input +v s ?v s (r1 + r2 + r3)||r l 2k? v ou t r l r1 2.26k ? r2 5k ? r3 2.26k ? (r2||40k ? ) + r1 + r3 (r2||40k ? ) rg 1 rg 2 1 16 13 12 11 3 2 8 7 10 6 9 00500-037 figure 37. gain of 2000 table 4. output gain resistor values output gain r2 r1, r3 nominal gain 2 5 k 2.26 k 2.02 5 1.05 k 2.05 k 5.01 10 1 k 4.42 k 10.1 input bias currents input bias currents are those currents necessary to bias the input transistors of a dc amplifier. bias currents are an additional source of input error and must be considered in a total error budget. the bias currents, when multiplied by the source resistance, appear as an offset voltage. what is of concern in calculating bias current errors is the change in bias current with respect to signal voltage and temperature. input offset current is the difference between the two input bias currents. the effect of offset current is an input offset voltage whose magnitude is the offset current times the source impedance imbalance. ad524 load + ? to power supply ground +v s ?v s 2 3 11 12 13 16 1 8 7 10 6 9 00500-038 figure 38. indirect ground returns for bias currentstransformer coupled ad524 load + ? +v s ?v s to power supply ground 2 8 7 10 6 9 3 11 12 13 16 1 00500-039 figure 39. indirect ground returns for bias currentsthermocouple ad524 load + v s ?v s to power supply ground 2 8 7 10 6 9 3 11 12 13 16 1 + ? 00500-040 figure 40. indirect ground returns for bias currentsCac-coupled although instrumentation amplifiers have differential inputs, there must be a return path for the bias currents. if this is not provided, those currents charge stray capacitances, causing the output to drift uncontrollably or to saturate. therefore, when amplifying floating input sources such as transformers and thermocouples, as well as ac-coupled sources, there must still be a dc path from each input to ground. common-mode rejection common-mode rejection is a measure of the change in output voltage when both inputs are changed equal amounts. these specifications are usually given for a full-range input voltage change and a specified source imbalance. common-mode rejection ratio (cmrr) is a ratio expression whereas common- mode rejection (cmr) is the logarithm of that ratio. for example, a cmrr of 10,000 corresponds to a cmr of 80 db. in an instrumentation amplifier, ac common-mode rejection is only as good as the differential phase shift. degradation of ac common-mode rejection is caused by unequal drops across differing track resistances and a differential phase shift due to varied stray capacitances or cable capacitances. in many applications, shielded cables are used to minimize noise. this technique can create common-mode rejection errors unless the shield is properly driven. figure 41 and figure 42 show active data guards that are configured to improve ac common-mode rejection by bootstrapping the capacitances of the input cabling, thus minimizing differential phase shift. reference ad524 100? ad711 g = 100 +input ?input v out + v s ?v s + ? rg 2 1 12 3 2 8 10 9 6 7 00500-041 figure 41. shield driver, g 100 reference ad524 100 ? ad712 +input ?input 100 ? v out +v s ?v s rg 1 rg 2 ?v s ? + 1 16 12 3 2 7 6 9 10 8 00500-042 figure 42. differential shield driver
ad524 rev. f | page 18 of 28 grounding many data acquisition components have two or more ground pins that are not connected together within the device. these grounds must be tied together at one point, usually at the system power-supply ground. ideally, a single solid ground would be desirable. however, because current flows through the ground wires and etch stripes of the circuit cards, and because these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the data acquisition components. separate ground returns should be provided to minimize the current flow in the path from the sensitive points to the system ground point. in this way, supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. because the output voltage is developed with respect to the potential on the reference terminal, an instrumentation amplifier can solve many grounding problems. digital p.s. +5v c ?15v analog p.s. ad574a c +15v 6 ad524 ad583 sample and hold dig com digital data output signal ground analog ground* output reference *if independent; otherwise, return amplifier reference to mecca at analog p.s. common. 1f 1f 1f 0.1 f 0.1 f 0.1 f 0.1 f 2 1 8 7 10 9 7 9 11 15 1 00500-043 figure 43. basic grounding practice sense terminal the sense terminal is the feedback point for the instrument amplifiers output amplifier. normally, it is connected to the instrument amplifier output. if heavy load currents are to be drawn through long leads, voltage drops due to current flowing through lead resistance can cause errors. the sense terminal can be wired to the instrument amplifier at the load, thus putting the ixr drops inside the loop and virtually eliminating this error source. v? v + x1 ad524 (ref) (sense) output current booster r l v in + v in ? 2 3 12 1 7 6 9 10 8 00500-044 figure 44. ad524 instrumentation amplifier with output current booster typically, ic instrumentation amplifiers are rated for a full 10 volt output swing into 2 k. in some applications, however, the need exists to drive more current into heavier loads. figure 44 shows how a high current booster may be connected inside the loop of an instrumentation amplifier to provide the required current boost without significantly degrading overall performance. nonlinearities and offset and gain inaccuracies of the buffer are minimized by the loop gain of the ad524 output amplifier. offset drift of the buffer is similarly reduced. reference terminal the reference terminal can be used to offset the output by up to 10 v. this is useful when the load is floating or does not share a ground with the rest of the system. it also provides a direct means of injecting a precise offset. it must be remembered that the total output swing is 10 v to be shared between signal and reference offset. when the ad524 is of the 3-amplifier configuration it is necessary that nearly zero impedance be presented to the reference terminal. any significant resistance from the reference terminal to ground increases the gain of the noninverting signal path, thereby upsetting the common-mode rejection of the ad524. in the ad524, a reference source resistance unbalances the cmr trim by the ratio of 20 k/r ref . for example, if the reference source impedance is 1 , cmr is reduced to 86 db (20 k/1 = 86 db). an operational amplifier can be used to provide that low impedance reference point, as shown in figure 45 . the input offset voltage characteristics of that amplifier adds directly to the output offset voltage performance of the instrumentation amplifier.
ad524 rev. f | page 19 of 28 ad524 ref sense load ad711 +input ?input r1 r1 === ( 1 + r1 ) 40,000 a2 + ? v x i l r g i l v x v in 2 3 13 1 10 9 6 00500-046 ad524 ref sense load ad711 v offset ?v s +v s v in + v in ? 2 8 10 9 6 7 3 12 1 0 0500-045 figure 45. use of reference terminal to provide output offset figure 46. voltage-to-current converter an instrumentation amplifier can be turned into a voltage- to-current converter by taking advantage of the sense and reference terminals, as shown in figure 46 . by establishing a reference at the low side of a current setting resistor, an output current may be defined as a function of input voltage, gain, and the value of that resistor. because only a small current is demanded at the input of the buffer amplifier (a2) the forced current, i l , largely flows through the load. offset and drift specifications of a2 must be added to the output offset and drift specifications of the ad524. y0 y2 y1 +5v c1 c2 a b +5v ?in +in out k1 k2 k3 d1 d2 d3 nc gain table abgain 0 0 1 1 0 1 0 1 10 1000 100 1 nc = no connect 1 2 3 4 5 6 7 8 20k ? 20k ? 20k? 404 ? 4.44k ? 20k ? 20k? 20k ? 40 ? protection protection 16 15 14 13 12 11 10 9 input offset trim analog common ?v s +v s k1 ? k3 = thermosen dm2c 4.5v coil d1 ? d3 = in4148 inputs gain range a1 ad524 logic common 10f 7407n buffer driver 74ls138 decoder g = 1000 k3 g = 100 k2 g = 10 k1 output offset trim relay shields r1 10k? +v s r2 10k ? 1f 35v 1 16 15 14 13 2 3 4 5 6 7 1 16 2 3 4 5 6 7 00500-047 figure 47. three-decade gain programmable amplifier
ad524 rev. f | page 20 of 28 programmable gain figure 47 shows the ad524 being used as a software program- mable gain amplifier. gain switching can be accomplished with mechanical switches such as dip switches or reed relays. it should be noted that the on resistance of the switch in series with the internal gain resistor becomes part of the gain equation and has an effect on gain accuracy. the ad524 can also be connected for gain in the output stage. figure 48 shows an ad711 used as an active attenuator in the output amplifiers feedback loop. the active attenuation presents very low impedance to the feedback resistors, therefore minimizing the common-mode rejection ratio degradation. to ?v ad524 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 20k? 20k? 20k? 404 ? 4.44k ? 20k? 20k? 20k ? 40? protection protection ?in +in (+input) (?input) 10k ? 10pf 20k ? ad711 ad7590 gnd 39.2k ? 28.7k ? 316k ? 1k? 1k? 1k? a4 a3a2 wr ?v s + v s 1f 35v input offset null +v s output offset null r2 10k? v out +v s ?v s v dd v ss v dd 15 13 11 9 2 14 12 10 34567 18 16 00500-048 + ? + ? figure 48. programmable output gain 2 1 10 6 ad524 dac a db0 256:1 20k ? g = 10 g = 100 g = 1000 4.44k ? 404 ? 40 ? protection 20k ? 20k ? 20k ? 20k ? 20k ? dac b db7 ad7528 9 16 11 12 protection 3 13 rg 1 rg 2 v b +input (?input) ?input (+input) v out cs wr 1/2 ad712 1/2 ad712 data inputs dac a /dac b +v s 4 14 7 15 16 6 18 5 17 3 2 1 19 20 00500-049 figure 49. programmable output gain using a dac another method for developing the switching scheme is to use a dac. the ad7528 dual dac, which acts essentially as a pair of switched resistive attenuators having high analog linearity and symmetrical bipolar transmission, is ideal in this application. the multiplying dacs advantage is that it can handle inputs of either polarity or zero without affecting the programmed gain. the circuit shown uses an ad7528 to set the gain (dac a) and to perform a fine adjustment (dac b). autozero circuits in many applications, it is necessary to provide very accurate data in high gain configurations. at room temperature, the offset effects can be nulled by the use of offset trim potenti- ometers. over the operating temperature range, however, offset nulling becomes a problem. the circuit of figure 50 shows a cmos dac operating in bipolar mode and connected to the reference terminal to provide software controllable offset adjustments.
ad524 rev. f | page 21 of 28 wr cs +input g = 10 ?input g = 100 g = 1000 ad7524 out2 39k ? ad589 msb lsb c1 gnd out1 ad524 +v s rg 1 rg 2 + ? ? + ? + ?v s v ref +v s +v s r5 20k ? r3 20k ? r4 10k ? ?v s r6 5k? 1/2 ad712 1/2 ad712 data inputs ?v s 2 8 7 10 6 9 16 13 12 11 3 1 7 6 5 4 1 8 2 3 3 13 12 11 4 15 14 16 1 2 00500-050 ad524c g = 100 10k? +10v 350? 350? 350? 350? 14-bit adc 0v to 2v f.s. +v s ?v s rg 1 rg 2 + ? 2 8 4 5 10 9 6 7 16 13 12 11 3 1 00500-052 figure 52. typical bridge application error budget analysis to illustrate how instrumentation amplifier specifications are applied, review a typical case where an ad524 is required to amplify the output of an unbalanced transducer. figure 52 shows a differential transducer, unbalanced by 100 , supplying a 0 mv to 20 mv signal to an ad524c. the output of the i a feeds a 14-bit adc with a 0 v to 2 v input voltage range. the operating temperature range is ?25c to +85c. therefore, the largest change in temperature, t, within the operating range is from ambient to +85c (85c ? 25c = 60c). figure 50. software controllable offset in many applications, complex software algorithms for autozero applications are not available. for those applications, figure 51 provides a hardware solution. ad524 14 15 16 13 gnd ch 1k ? zero pulse ad7510kd ad711 a1 a2 a3 a4 v dd v ss 200s 910 11 12 ?v s v out 0.1f low leakage +v s rg 1 rg 2 2 8 7 10 6 9 16 13 12 11 3 1 8 1 2 ? + ? + 00500-051 in many applications, differential linearity and resolution are of prime importance in cases where the absolute value of a variable is less important than changes in value. in these applications, only the irreducible errors (45 ppm = 0.004%) are significant. further- more, if a system has an intelligent processor monitoring the analog-to-digital output, the addition of an autogain/autozero cycle removes all reducible errors and may eliminate the require- ment for initial calibration. this also reduces errors to 0.004%. figure 51. autozero circuit
ad524 rev. f | page 22 of 28 table 5. error budget analysis error source ad524c specifications calculation effect on absolute accuracy at t a = 25c effect on absolute accuracy at t a = 85c effect on resolution gain error 0.25% 0.25% = 2500 ppm 2500 ppm 2500 ppm C gain instability 25 ppm (25 pp m/c)(60c) = 1500 ppm C 1500 ppm C gain nonlinearity 0.003% 0.003% = 30 ppm C C 30 ppm input offset voltage 50 v, rti 50 v/20 mv = 2500 ppm 2500 ppm 2500 ppm C input offset voltage drift 0.5 v/c C (0.5 v/c)(60c) = 30 v 30 v/20 mv = 1500 ppm C 1500 ppm C output offset voltage 1 2.0 mv 2.0 mv/20 mv = 1000 ppm 1000 ppm 1000 ppm C output offset voltage drift 1 25 v/c (25 v/c)(60c)= 1500 v 1500 v/20 mv = 750 ppm C 750 ppm C bias current-source imbalance error 15 na (15 na)(100 ) = 1.5 v 1.5 v/20 mv = 75 ppm 75 ppm 75 ppm C bias current-source imbalance drift 100 pa/c (100 pa/c)(100 )(60c) = 0.6 v 0.6 v/20 mv = 30 ppm C 30 ppm C offset current-source imbalance error 10 na (10 na)(100 ) = 1 v 1 v/20 mv = 50 ppm 50 ppm 50 ppm C offset current-source imbalance drift 100 pa/c (100 pa/c)(100 )(60c) = 0.6 v 0.6 v/20 mv = 30 ppm C 30 ppm C offset current-source resistance-error 10 na (10 na)(175 ) = 3.5 v 3.5 v/20 mv = 87.5 ppm 87.5 ppm 87.5 ppm C offset current-source resistance-drift 100 pa/c (100 pa/c)(175 )(60c) = 1 v 1 v/20 mv = 50 ppm C 50 ppm C common mode rejection 5 v dc 115 db 115 db = 1.8 ppm 5 v = 8.8 v 8.8 v/20 mv = 444 ppm 444 ppm 444 ppm C noise, rti (0.1 hz to 10 hz) 0.3 v p-p 0.3 v p-p/20 mv = 15 ppm C C 15 ppm total error 6656.5 ppm 10516.5 ppm 45 ppm 1 output offset volt age and output offset voltage drift are given as rti figures.
ad524 rev. f | page 23 of 28 figure 53 shows a simple application in which the variation of the cold-junction voltage of a type j thermocouple-iron constantan is compensated for by a voltage developed in series by the temperature-sensitive output current of an ad590 semiconductor temperature sensor. ad524 iron constantan ad590 cu 52.3 ? 8.66k ? 1k? e o 2.5v ad580 7.5v g = 100 ? 2.5v 1 + 52.3 ? r type j k e t s, r r a nominal value reference junction +15c < t a < +35c 52.3 ? 41.2 ? 61.4 ? 40.2 ? 5.76 ? +v s i a t a v a +v s + ? ?v s output amplifier or meter r t nominal value 9135 ? r a e o = v t ? v a + 52.3 ? i a + 2.5v measuring junction = v t ~ v t 0 0500-053 figure 53. cold-junction compensation the circuit is calibrated by adjusting r t for proper output voltage with the measuring junction at a known reference temperature and the circuit near 25c. if resistors with low temperature coefficients are used, compensation accuracy is to within 0.5c, for temperatures between +15c and +35c. other thermocouple types may be accommodated with the standard resistance values shown in table 5 . for other ranges of ambient temperature, the equation in figure 53 may be solved for the optimum values of r t and r a . the microprocessor controlled data acquisition system shown in figure 54 includes both autozero and autogain capability. by dedicating two of the differential inputs, one to ground and one to the a/d reference, the proper program calibration cycles can eliminate both initial accuracy errors and accuracy errors over temperature. the autozero cycle, in this application, converts a number that appears to be ground and then writes that same number (8-bit) to the ad7524, which eliminates the zero error. because its output has an inverted scale, the autogain cycle converts the a/d reference and compares it with full scale. a multiplicative correction factor is then computed and applied to subsequent readings. for a comprehensive study of instrumentation amplifier design and applications, refer to the designers guide to instrumentation amplifiers (3 rd edition) , available free from analog devices, inc. ad524 ad7524 ad574a ad583 agnd 20k ? 10k ? 5k? ad7507 control decode latch address bus a0, a2, en, a1 v in v ref micro- processor + ? rg 2 rg 1 ?v ref 20k ? 1/2 ad712 1/2 ad712 ? + ? + 2 10 6 9 16 13 12 11 3 1 0 0500-054 figure 54. microprocessor controlled data acquisition system
ad524 rev. f | page 24 of 28 outline dimensions 16 1 8 9 0.310 (7.87) 0.220 (5.59) pin 1 0.080 (2.03) max 0.005 (0.13) min seating plane 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.100 (2.54) bsc 0.150 (3.81) min 0.840 (21.34) max 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. figure 55. 16-lead side-brazed ceramic dual in-line [sbdip] (d-16) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off i nch equivalents for reference only and are not appropriate for use in design. 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) ref 0.200 (5.08) ref 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 022106-a figure 56. 20-terminal cerami c leadless chip carrier [lcc] (e-20) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 57. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches)
ad524 rev. f | page 25 of 28 ordering guide model temperature range package description package option ad524ad ?40c to +85c 16-lead sbdip d-16 ad524adz 1 ?40c to +85c 16-lead sbdip d-16 ad524ae ?40c to +85c 20-terminal lcc e-20 ad524ar-16 ?40c to +85c 16-lead soic_w rw-16 ad524ar-16-reel ?40c to +85c 16-lead soic_w, 13" tape and reel rw-16 ad524ar-16-reel7 ?40c to +85c 16-lead soic_w, 7" tape and reel rw-16 ad524arz-16 1 ?40c to +85c 16-lead soic_w rw-16 ad524arz-16-reel7 1 ?40c to +85c 16-lead soic_w, 7tape and reel rw-16 ad524bd ?40c to +85c 16-lead sbdip d-16 ad524bdz 1 ?40c to +85c 16-lead sbdip d-16 ad524be ?40c to +85c 20-terminal lcc e-20 ad524cd ?40c to +85c 16-lead sbdip d-16 ad524cdz 1 ?40c to +85c 16-lead sbdip d-16 ad524sd ?55c to +125c 16-lead sbdip d-16 ad524sd/883b ?55c to +125c 16-lead sbdip d-16 5962-8853901ea 2 ?55c to +125c 16-lead sbdip d-16 ad524se/883b ?55c to +125c 20-terminal lcc e-20 ad524schips ?55c to +125c die 1 z = rohs compliant part. 2 refer to the official desc dr awing for tested specifications.
ad524 rev. f | page 26 of 28 notes
ad524 rev. f | page 27 of 28 notes
ad524 rev. f | page 28 of 28 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00500-0-11/07(f)

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